The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device having a wiring board.
There has been proposed a technique in which an opening portion is formed on a solder resist layer covering the outermost conductive layer, a plating post is formed by filling a plating in a space defined by the side walls of the opening portion of the solder resist layer and the surface of the conductive layer, and a soldering member is formed on the surface of the plating post (see, e.g., Japanese Unexamined Patent Publication No. 2002-368398 (FIG. 5)).